The resetting of a data storage array typically involves clearing or “zeroing” the contents of all of the storage locations or cells of the data storage array. This is achieved by addressing each storage location and writing a “0” into each cell in response to the occurrence of a reset control signal. A common method of resetting the data storage array to “0” or “1” is by selecting all word lines of the data storage array and forcing all bit lines to a reference potential. (The reference potential is usually ground).
According to another method of resetting a data storage array, the common ground of data storage array is raised to the value of supply voltage VDD as shown in FIG. 1. VGND of the first section of cells of the data storage array is driven to a voltage VDD by applying of a reset control signal CLEAR external to the data storage array. Transistor 106 passes logic “1” to node A, which is initially at logic “0”. Transistor 106 is turned off and transistor 104 is turned ON, which further assists in initializing the data storage array after a reset control signal has been encountered.